QFN packaging

While logic chips are driving to massive pin counts, huge power consumption, and ever larger BGA package structures, another class of devices is driving very different test requirements. For the majority of Analog, Mixed-Signal, Power, and RF devices, power and pin count take a back seat to electrical performance and reliability. Fabricated primarily on legacy ( >16nm ) process nodes, these devices tend to have small numbers of I/O connections and ganged power connections. To improve electrical performance while reducing the size, weight, and footprint of these devices, device manufacturers make use of QFN packages to achieve their goals.
 
QFN packages make use of traditional wire bonding and molding encapsulation techniques to protect the silicon die. What makes them stand out is their use of “near chip scale” pad layouts on the periphery, combined with a large “ePad” or “exposed paddle.” With electrical pads fully contained inside the outline of the molded plastic package body, QFN’s eliminate many of the handling and reliability challenges of their QFP and SOIC predecessors. When a QFN is soldered onto a PCB, the connection is as short as possible, and – aside from certain CTE（Coefficient of Termal Expansion） considerations – extremely robust. With a large – actually huge – ground pad in the center of the rectangular package body, QFN’s offer not only excellent electrical performance, but greatly improved thermal dissipation. Instead of the IC’s heat needing to escape upward through the package body, in a QFN ePad the heat can be wicked downward into the PCB to thermal vias, greatly improving stability and performance.
 
To test QFN devices, test operations needs must balance their cost targets for robust and reliable performance over hundreds of thousand of insertions with their performance requirements of extremely clean signal paths. In many cases, the Device Under Test (DUT) will have RF requirements exceeding 10GHz or more, inductance specs that must be carefully managed, and very low Contact Resistance targets. To balance these needs, engineers look for a test socket solution with a short, highly controlled signal path and a robust mechanical structure. One key element of the mechanical structure that warrants special consideration is the wear rate on the surface pad of the PCB Load Board used to connect the socket to the ATE test system. With Load Board costs routinely exceeding $50,000 to $75,000, it is imperative that the socket actuation cause as little damage to the surface pads as possible. If the test socket causes pad damage, the test operations team may need to re-plate the PCB’s surface pads, or, worse, replace the entire PCB.

Smiths Interconnect’s  Kepler test socket delivers a proven solution for test engineers and test operations managers that balance both the electrical targets and the HVM production requirements for today’s advanced QFN-packaged ICs. With a 2-Axis of motion a single stroke, providing best-in-class electrical length, inductance, and contact resistance, Kepler meets all of the industry’s key care-abouts for sub-20GHz test applications. The X,Y-Axis motion of the contact breaks surface oxides, with the same impact on PCB Load Board pads as a vertical spring probe, allowing for hundreds of thousands of cycles with little to zero maintenance. Footprint-compatible with existing QFN offset socket solutions, Kepler can be implemented in short order for demanding high-volume IC applications.